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10 mhz, 14.5 nv/hz, rail - to - rail i/o, zero input crossover distortion amplifier data sheet ada4500 - 2 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.470 0 ? 2012 analog devices, inc. all rights reserved. technical support www.analog.com features power supply rejection ratio ( psrr ) : 98 db minimum common - mode rejection ratio ( cmrr ) : 95 db minimum offset voltage: 120 v maximum single - s upply operation : 2.7 v to 5.5 v dual - s upply operation : 1.35 v to 2.75 v wide b andwidth: 10 mhz rail - to - r ail i nput and o utput low n oise 2 v p - p from 0.1 hz to 10 hz 1 4.5 nv/hz at 1 khz very l ow i nput b ias c urrent: 2 pa maximum applications pressure and p osition s ensors remote s ecurity medical m onitors process control s hazard d etectors photo d iode applications pin configuration out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4500-2 top view (not to scale) 10617-001 figure 1. 8- lead msop pin configuration for more information on the pin connections, see the pin configurations and function descriptions section 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 0 5 4 3 2 1 v os (v) v cm (v) ada4500-2 v sy = 5.0v 10617-004 figure 2. the ada4500 - 2 eliminates crossover distortion acr oss its full supply range g eneral d escription the ada4500 - 2 is a dual 10 mhz, 14.5 nv/hz, low power amplifier featuring rail - to - rail input and output swings while operating from a 2.7 v to 5.5 v single power supply. compatible with industry - standard nominal voltages of + 3.0 v, + 3.3 v, + 5.0 v, and 2.5 v. employing a novel zero - crossover distortion circuit topology, this amplifier offers high linearity over the full, rail - to - rail input common - mode range, with excellent power supply rejection ratio (psrr) and common - mode rejection ratio (cmrr) performance without the crossover di stortion seen with the traditional complementary rail - to - rail input stage. the resulting op amp also has excellent precision, wide bandwidth, and very low bias current. this combination of features makes the ada4500 - 2 an ideal choice for precision sensor applications because it minimizes errors due to power supply variation and maintains high cmrr over the full input voltage range. the ada4500 - 2 is also an ex cellent amplifier for driving analog - to - digital converters (adcs) because the output does not distort with the common - mode voltage , which enabl es the adc to u s e its full input voltage range, maximizing the dynamic range of the conversion subsystem. many a pplications such as sensors, handheld instrumentation, precision signal conditioning, and patient monitors can benefit from the features of the ada4500 - 2 . the ada4500 - 2 is specified for the extended industrial temperature range (?40c to +125c) and available in the standard 8 - lead msop and 8 - lead lfcsp packages .
ada4500- 2 data sheet rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 pin configuration ............................................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 v sy = 2.7 v electrical characteristics ........................................ 3 v sy = 5.0 v electrical characteristics ........................................ 5 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 19 rail - to - rail output .................................................................... 19 rail - to - rail input (rri) ............................................................ 19 zero cross - over distortion ..................................................... 19 overload recovery ..................................................................... 20 power - on current profile ......................................................... 21 applications information .............................................................. 22 resistance and capacitance sensor circuit ............................ 22 adaptive single - ended - to - differential signal converter ..... 22 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 10 /12 C rev . 0 to rev. a changes to ordering guide .......................................................... 24 10 /12 C revision 0: initial version
data sheet ada4500- 2 rev. a | page 3 of 24 specifications v s y = 2.7 v electrical character istics v s y = 2.7 v, v cm = v s y /2, t a = 25 c, unless otherwise specified . table 1 . parameter symbol test conditions /conditions min typ max unit input characteristics offset voltage v os 120 v ? 40 c < t a < +125c 700 v offset voltage drift tc v os ?40c < t a < +125c 0.8 5.5 v/c input bias current i b 0.3 1 pa ?40c < t a < +125c 170 pa input offset current i os 0.3 1 pa ?40c < t a < +125c 20 pa input voltage range ivr ?40c < t a < +125c v ? v+ v common - mode rejection ratio cmrr v cm = v? to v+ 95 110 db ?40c < t a < +125c 90 db v cm = [(v?) ? 0.2 v] to [(v+) + 0.2 v ] 90 110 db ?40c < t a < +125c 80 db large signal voltage gain a vo r l = 2 k?, [(v?) + 0.05 v] < v out < [(v+) ? 0.05 v] 100 110 db ?40c < t a < +125c 100 db r l = 10 k?, [(v?) + 0.05 v] < v out < [(v+) ? 0.05 v] 105 120 db ?40c < t a < +125c 105 db input capacitance common mode c incm 5 pf differential c indm 1.7 pf inp ut resistance r in common mode and differential mode 400 g ? output characteristics output voltage high v oh r l = 10 k? to v ? 2.685 2.695 v ?40c < t a < +125c 2.6 8 v r l = 2 k? to v ? 2.65 2.68 v ?40c < t a < +125c 2.65 v output volt age low v ol r l = 10 k ? to v+ 3 5 mv ?40c < t a < +125c 10 mv r l = 2 k ? to v+ 13 20 mv ?40c < t a < +125c 25 mv short circuit limit i sc sourcing , v out shorted to v ? 26 ma sinking , v out shorted to v+ ? 48 ma closed - loop impedance z ou t f = 10 mhz, a v = 1 70 ? power supply power supply rejection ratio psrr v s y = 2.7 v to 5.5 v 98 119 db ?40c to +125c 94 db supply current per amplifier i sy i o = 0 ma 1.5 1.65 ma ?40c < t a < +125c 1.7 ma dynamic performance slew rate sr r l = 10 k ? , c l = 30 pf, a v = + 1, v in = v sy 5.5 v/s r l = 10 k ? , c l = 30 pf, a v = ? 1, v in = v sy 8.7 v/s gain bandwidth product gbp v in = 5 mv p - p, r l = 10 k ? , a v = + 100 10.1 mhz unity gain crossover ugc v in = 5 mv p - p, r l = 10 k ? , a v = + 1 10.3 mhz ? 3 db bandwidth ? 3 db v in = 5 mv p - p, r l = 10 k ? , a v = ? 1 18.4 mhz phase margin m v in = 5 mv p - p, r l = 10 k?, c l = 20 pf , a v = +1 52 degrees settling time to 0.1% t s v in = 2 v p - p, r l = 10 k?, c l = 10 pf, a v = ?1 1 s
ada4500- 2 data sheet rev. a | page 4 of 24 parameter symbol test conditions /conditions min typ max unit noise performance total harmonic distortion + noise thd+n g = 1, f = 10 hz to 20 khz, v in = 0.7 v rms at 1 khz bandwidth = 80 khz 0.0006 % bandwidth = 500 khz 0.001 % peak - to - peak noise e n p - p f = 0.1 hz to 10 hz 3 v p - p voltage noise d ensity e n f = 1 khz 14.5 nv/hz current noise density i n f = 1 khz <0.5 fa/hz
data sheet ada4500- 2 rev. a | page 5 of 24 v s y = 5 .0 v electrical character istics v s y = 5 .0 v, v cm = v s y /2, t a = 25 c, unless otherwise specified . table 2 . parameter symbol test con ditions /comments min typ max unit input characteristics offset voltage v os 120 v ? 40c < t a < +125c 700 v offset voltage drift tc v os ?40c < t a < +125c 0.9 5.5 v/c input bias current i b 0.7 2 pa ?40c < t a < +125c 190 pa i nput offset current i os 0.3 3 pa ?40c < t a < +125c 20 pa input voltage range ivr ?40c < t a < +125c v ? v+ v common - mode rejection ratio cmrr v cm = v? to v+ 95 115 db ?40c < t a < +125c 95 db v cm = [(v?) ? 0.2 v] to [(v+) + 0.2 v ] 95 115 db ?40c < t a < +125c 84 db large signal voltage gain a vo r l = 2 k?, [(v?) + 0.05 v] < v out < [(v+) ? 0.05 v] 105 110 db ?40c < t a < +125c 80 db r l = 10 k?, [(v?) + 0.05 v] < v out < [(v+) ? 0.05 v] 110 120 db ?40c < t a < +125c 110 db input capacitance common mode c incm 5 pf differential c indm 1.7 pf input resistance r in common mode and differential mode 400 g ? output characteristics output voltage high v oh r l = 10 k? to v ? 4.9 75 4.99 v ?40c < t a < +125c 4.97 v r l = 2 k? to v ? 4.95 4.97 v ?40c < t a < +125c 4.95 v output voltage low v ol r l = 10 k? to v+ 7 15 mv ?40c < t a < +125c 20 mv r l = 2 k? to v+ 24 40 mv ?40c < t a < +125c 50 mv short circuit limit i sc sourcing , v out shorted to v? 75 ma sinking , v out shorted to v+ ? 75 ma closed - loop impedance z out f = 10 mhz, a v = + 1 60 ? power supply power supply rejection ratio psrr v s y = 2.7 v to 5.5 v 98 119 db ?40c to +125c 94 db supply current pe r amplifier i sy i o = 0 ma 1.55 1.75 ma ?40c < t a < +125c 1.8 ma dynamic performance slew rate sr r l = 10 k? , c l = 30 pf, a v = +1, v in = v sy 5.5 v/s r l = 10 k? , c l = 30 pf, a v = ? 1, v in = v sy 8.7 v/s gain bandwidth product gbp v in = 5 mv p - p, r l = 10 k? , a v = + 100 10 mhz unity gain crossover ugc v in = 5 mv p - p, r l = 10 k? , a v = + 1 10.5 mhz ? 3 db bandwidth ?3 db v in = 5 mv p - p, r l = 10 k? , a v = ? 1 19.2 mhz phase margin m v in = 5 mv p - p, r l = 10 k?, c l = 20 pf , a v = +1 57 degrees settling time to 0.1% t s v in = 4 v p - p, r l = 10 k?, c l = 10 pf, a v = ?1 1 s
ada4500- 2 data sheet rev. a | page 6 of 24 parameter symbol test con ditions /comments min typ max unit noise performance total harmonic distortion + noise thd+n g = 1, f = 20 hz to 20 khz, v in = 1.4 v rms at 1 khz bandwidth = 80 khz 0.0004 % bandwidth = 500 khz 0.0008 % peak - to - peak noise e n p - p f = 0.1 hz to 10 hz 2 v p - p voltage noise density e n f = 1 khz 14.5 nv/hz current noise density i n f = 1 khz <0.5 fa/hz
data sheet ada4500- 2 rev. a | page 7 of 24 absolute maximum rat ings table 3 . parameter ratin g supply voltage 6 v input voltage (v ? ) ? 0.2 v to (v+) + 0.2 v differential input voltage 1 (v ? ) ? 0.2 v to (v+) + 0.2 v output short - circuit duration indefinite storage temperature range ? 65c to +150c operating temperature range ?40c to +125c j unction temperature range ?65c to +150c lead temperature (soldering, 60 sec) 300c 1 differential input voltage is limited to 5 .6 v or the supply voltage + 0.6 v , whichever is less. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating con ditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jc unit 8 - lead msop (rm-8) 1 142 45 c/w 8 - lead lfcsp (cp - 8 - 12 ) 2, 3 85 2 c/w 1 thermal numbers were simulated on a 4 - layer jedec printed circuit board ( pcb ). 2 thermals numbers were simulated on a 4 layer jedec pcb with the exposed pad soldered to the pcb. 3 jc was simulated at the exposed pad on the bottom of the package. esd caution
ada4500- 2 data sheet rev. a | page 8 of 24 pin configurations a nd function descript ions out a 1 ?in a 2 +in a 3 v? 4 v+ 8 out b 7 ?in b 6 +in b 5 ada4500-2 top view (not to scale) 10617-400 figure 3. 8 - lead msop pin configuration 10617-200 3 +in a 4 v? 1 out a 2 ?in a 6 ?in b 5 +in b 8 v+ 7 out b ada4500-2 top view (not to scale) notes 1. connect the exposed pad to v? or leave it unconnected. figure 4. 8 - lead lfcsp pin configuration table 5 . 8 -l ead msop and 8 - lead lfcsp pin function descriptions pin o. mnemonic description 1 out a output, channel a . 2 ?in a inverting input, channel a . 3 +in a noninverting input, channel a . 4 v? negative supply voltage . 5 +in b noninverting input, channel b . 6 ? in b inverting input, channel b . 7 out b output, channel b . 8 v+ positive supply voltage . epad for the lfcsp p ackage only , c onnect the exposed pad to v? or leave it unconnected .
data sheet ada4500- 2 rev. a | page 9 of 24 typical performance characteristics t a = 25 c, unless otherwise noted. 100 90 80 70 60 50 40 30 20 10 0 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 number of units v os (v) ada4500-2 v sy = 2.7v v cm = v sy /2 10617-002 f igure 5 . input offset voltage distribution , v s y = 2.7 v 35 30 25 20 15 10 5 0 0 8.75 7.50 6.25 5.00 3.75 2.50 1.25 number of units tcv os (v/c) ada4500-2 v sy = 2.7v v cm = v sy /2 C40c t a +125c 10617-006 figure 6 . input offset voltage drift distribution , v s y = 2.7 v 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 ?0.2 2.8 2.3 1.8 1.3 0.8 0.3 v os (v) v cm (v) ada4500-2 v sy = 2.7v 10617-007 figure 7 . input offset voltage (v os ) vs. common - mode voltage (v cm ), v s y = 2.7 v 100 90 80 70 60 50 40 30 20 10 0 ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 120 number of units v os (v) ada4500-2 v sy = 5.0v v cm = v sy /2 10617-005 figure 8 . input offset voltage distribution , v s y = 5 .0 v 35 30 25 20 15 10 5 0 0 8.75 7.50 6.25 5.00 3.75 2.50 1.25 number of units tcv os (v/c) ada4500-2 v sy = 5.0v v cm = v sy /2 C40c t a +125c 10617-003 figure 9 . input offset voltage drift distribution , v s y = 5 .0 v ?0.2 2.8 4.8 3.8 1.8 0.8 100 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 v os (v) v cm (v) ada4500-2 v sy = 5.0v 10617-004 figure 10 . input offset voltage (v os ) vs. common - mode voltage (v cm ), v sy = 5.0 v
ada4500- 2 data sheet rev. a | page 10 of 24 t a = 25 c, unless otherwise noted. 100 ?40 ?20 0 20 40 60 80 ?50 ?25 0 25 50 75 100 125 150 i b (pa) temperature (c) ada4500-2 v sy = 2.7v v cm = v sy /2 i b + i b ? 10617-008 figure 11 . input bias current (i b ) vs. temperature , v s y = 2.7 v 0 3.0 2.5 2.0 1.5 1.0 0.5 i b (pa) v cm (v) ada4500-2 v sy = 2.7v 10617-012 100 ?40 ?20 0 20 40 60 80 figure 12 . input bias current (i b ) vs. common - mode voltage (v cm ), v sy = 2.7 v 10k 1k 100 10 1 0.1 0.001 100 10 1 0.1 0.01 output (v oh ) to supply (mv) load current (ma) ada4500-2 v sy = 2.7v sourcing output current 10617-010 ?40c +25c +125c figure 13 . output voltage (v oh ) to supply rail vs. load current , v s y = 2.7 v 100 ?40 ?20 0 20 40 60 80 ?50 ?25 0 25 50 75 100 125 150 i b (pa) temperature (c) ada4500-2 v sy = 5.0v v cm = v sy /2 i b + i b ? 10617-0 1 1 figure 14 . input bias current (i b ) vs. temperature , v s y = 5 .0 v 100 ?40 ?20 0 20 40 60 80 0 5 4 3 2 1 i b (pa) v cm (v) ada4500-2 v sy = 5.0v 10617-009 figure 15 . input bias current (i b ) vs. common - mode voltage (v cm ), v sy = 5.0 v 10k 1k 100 10 1 0.1 0.001 100 10 1 0.1 0.01 output (v oh ) to supply (mv) load current (ma) ada4500-2 v sy = 5.0v sourcing output current 10617-013 ?40c +25c +125c figure 16 . output voltage (v oh ) to supply rail vs. load current , v s y = 5 .0 v
data sheet ada4500- 2 rev. a | page 11 of 24 t a = 25 c, unless otherwise noted. 10k 1k 100 10 1 0.1 0.001 100 10 1 0.1 0.01 output (v ol ) to supply (mv) load current (ma) ada4500-2 v sy = 2.7v sinking output current 10617-014 ?40c +25c +125c figure 17 . output voltage (v ol ) to supply rail vs. temperature , v sy = 2.7 v 50 40 30 20 10 0 ?50 ?25 0 25 50 75 100 125 150 output (v oh ) to supply (mv) temperature (c) ada4500-2 v sy = 2.7v r l = 2k? r l = 10k? 10617-015 figure 18 . output voltage (v oh ) to supply rail vs. temperature , v sy = 2.7 v 20 15 10 5 0 ?50 ?25 0 25 50 75 100 125 150 output (v ol ) to supply (mv) temperature (c) ada4500-2 v sy = 2.7v r l = 2k? r l = 10k? 10617-016 figure 19 . output voltage (v ol ) to supply rail vs. temperature , v sy = 2.7 v 10k 1k 100 10 1 0.1 0.001 100 10 1 0.1 0.01 output (v ol ) to supply (mv) load current (ma) ada4500-2 v sy = 5.0v sinking output current 10617-017 ?40c +25c +125c figure 20 . output v oltage (v ol ) to supply rail vs. load current , v sy = 5 .0 v 50 40 30 20 10 0 ?50 ?25 0 25 50 75 100 125 150 output (v oh ) to supply (mv) temperature (c) ada4500-2 v sy = 5.0v r l = 2k? r l = 10k? 10617-018 figure 21 . output voltage (v oh ) to supply rail vs. temperature , v sy = 5.0 v 50 40 30 20 10 0 ?50 ?25 0 25 50 75 100 125 150 output (v ol ) to supply (mv) temperature (c) ada4500-2 v sy = 5.0v r l = 2k? r l = 10k? 10617-019 figure 22 . output voltage (v ol ) to supply rail vs. temperatur e , v sy = 5.0 v
ada4500- 2 data sheet rev. a | page 12 of 24 t a = 25 c, unless otherwise noted. 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 supply current per amp (ma) supply voltage (v) +25c +85c ?40c ada4500-2 +125c 10617-020 figure 23 . supply current per amp vs. supply voltage gain (db) phase (degrees) frequency (hz) r l = 10k c l = 20pf v sy = 2.7v v cm = v sy /2 ada4500-2 150 100 50 0 ?50 ?100 150 100 50 0 ?50 ?100 100 1k 10k 100k 1m 10m 100m phase gain 10617-021 figure 24 . open - loop gain and phase vs. frequency , v s y = 2.7 v 60 40 20 0 ?20 50 30 10 ?10 10 100 1k 10k 100k 1m 10m 100m closed-loop gain (db) frequency (hz) ada4500-2 v sy = 2.7v v cm = v sy /2 a v = +100 a v = +10 a v = +1 10617-022 figure 25 . closed loop gain vs. frequency , v s y = 2.7 v 2.0 1.8 1.6 1.4 1.2 1.0 ?50 ?25 0 25 50 75 100 150 125 supply current per amp (ma) temperature (c) v sy = 2.5v v sy = 1.35v 10617-023 ada4500-2 figure 26 . supply current per amp vs. temperature gain (db) phase (degrees) frequency (hz) r l = 10k c l = 20pf v sy = 5.0v v cm = v sy /2 phase gain 10617-024 ada4500-2 150 100 50 0 ?50 ?100 150 100 50 0 ?50 ?100 100 1k 10k 100k 1m 10m 100m figure 27 . open - l oop gain and phase vs. frequency, v sy = 5.0 v 60 40 20 0 ?20 50 30 10 ?10 10 100 1k 10k 100k 1m 10m 100m closed-loop gain (db) frequency (hz) ada4500-2 v sy = 5.0v v cm = v sy /2 a v = +100 a v = +10 a v = +1 10617-025 figure 28 . closed - loop gain vs. frequency , v sy = 5.0 v
data sheet ada4500- 2 rev. a | page 13 of 24 t a = 25 c, unless otherwise noted. cmrr (db) frequency (hz) ada4500-2 v sy = 2.7v v cm = v sy /2 160 140 120 100 80 60 40 20 0 100 1k 10k 100k 1m 10m 100m 10617-100 figure 29 . cmrr vs. frequency, v sy = 2.7 v psrr (db) frequency (hz) ada4500-2 v sy = 2.7v v cm = v sy /2 140 120 100 80 60 40 20 ?20 0 100 1k 10k 100k 1m 10m 100m psrr+ psrr? 10617-026 figure 30 . psrr vs. frequency , v sy = 2.7 v 1k 100 10 1 0.1 0.001 0.01 100 100m 10m 1m 100k 10k 1k z out (?) frequency (hz) ada4500-2 v sy = 2.7v v cm = v sy /2 10617-027 a v = +100 a v = +10 a v = +1 f igure 31 . closed loop output impedance (z out ) vs. frequency , v sy = 2.7 v cmrr (db) frequency (hz) ada4500-2 v sy = 5.0v v cm = v sy /2 140 120 100 80 60 40 20 0 100 1k 10k 100k 1m 10m 100m 10617-101 figure 32 . cmrr vs. frequency , v sy = 5.0 v psrr (db) frequency (hz) 140 120 100 80 60 40 20 ?20 0 100 1k 10k 100k 1m 10m 100m psrr+ psrr? 10617-029 ada4500-2 v sy = 5.0v v cm = v sy /2 figure 33 . psrr vs. frequency , v sy = 5.0 v 1k 100 10 1 0.1 0.001 0.01 100 100m 10m 1m 100k 10k 1k z out (?) frequency (hz) ada4500-2 v sy = 5.0v v cm = v sy /2 10617-030 a v = +100 a v = +10 a v = +1 figure 34 . closed loop output impedance (z out ) vs. frequency , v sy = 5.0 v
ada4500- 2 data sheet rev. a | page 14 of 24 t a = 25 c, unless otherwise noted. voltage (0.5v/div) time (400ns/div) ada4500-2 v sy = 2.7v v cm = v sy /2 v in = 2v p-p a v = +1 r l = 10k c l = 100pf 10617-028 figure 35 . large signal transient response , v sy = 2.7 v voltage (50mv/div) time (200ns/div) ada4500-2 v sy = 2.7v v cm = v sy /2 v in = 100mv p-p a v = +1 r l = 10k c l = 100pf 10617-032 figure 36 . s mall signal transient response , v sy = 2.7 v overshoot (%) load capacitance (pf) 80 70 60 50 40 30 20 0 10 1 10 100 os+ os? ada4500-2 v sy = 2.7v v cm = v sy /2 v in = 100mv p-p a v = +1 r l = 10k 10617-033 figure 37 . small signal overshoot vs. load capacitance , v sy = 2.7 v voltage (1v/div) time (200ns/div) ada4500-2 v sy = 5.0v v cm = v sy /2 v in = 4v p-p a v = +1 r l = 10k c l = 100pf 10617-031 figure 38 . large signal transient response , v sy = 5 .0 v voltage (50mv/div) time (200ns/div) ada4500-2 v sy = 5.0v v cm = v sy /2 v in = 100mv p-p a v = +1 r l = 10k c l = 100pf 10617-035 figure 39 . small signal transient response , v sy = 5.0 v overshoot (%) load capacitance (pf) 80 70 60 50 40 30 20 0 10 1 10 100 os+ os? ada4500-2 v sy = 5.0v v cm = v sy /2 v in = 100mv p-p a v = +1 r l = 10k 10617-036 figure 40 . small signal overshoot vs. load capacitance , v sy = 5.0 v
data sheet ada4500- 2 rev. a | page 15 of 24 t a = 25 c, unless otherwise noted. input voltage (v) output voltage (v) time (2s/div) ada4500-2 v sy = 1.35v v in = 50mv p-p a v = ?100 r l = 10k c l = 100pf 0.05 0 ?0.05 ?0.10 1.5 1.0 0.5 0 ?0.5 input output 10617-034 figure 41 . positive overload recovery , v sy = 1.35 v input voltage (v) output voltage (v) time (2s/div) ada4500-2 v sy = 1.35v v in = 50mv p-p a v = ?100 r l = 10k c l = 100pf 0.10 0.05 0 ?0.05 0.5 0 ?0.5 ?1.0 ?1.5 input output 10617-038 figure 42 . negative overload recovery , v sy = 1.35 v input voltage (v) output voltage (v) time (2s/div) ada4500-2 v sy = 2.5v v in = 100mv p-p a v = ?100 r l = 10k c l = 100pf 0.1 0 ?0.1 ?0.2 3 2 1 0 ?1 input output 10617-037 figure 43 . positive overload recovery , v sy = 2.5 v input voltage (v) output voltage (v) time (2s/div) ada4500-2 v sy = 2.5v v in = 100mv p-p a v = ?100 r l = 10k c l = 100pf 0.2 0.1 0 ?0.1 1 0 ?1 ?2 ?3 input output 10617-041 figure 44 . negative overload reco very , v sy = 2.5 v
ada4500- 2 data sheet rev. a | page 16 of 24 t a = 25 c, unless otherwise noted. input voltage (1v/div) time (400ns/div) ada4500-2 v sy = 2.7v v cm = v sy /2 r l = 10k c l = 10pf dut a v = ?1 error band post gain = 20 input output ?20mv 0 +20mv 10617-039 figure 45 . positive settling time to 0.1% , v sy = 2.7 v input voltage (1v/div) time (400ns/div) ada4500-2 v sy = 2.7v v cm = v sy /2 r l = 10k c l = 10pf dut a v = ?1 error band post gain = 20 input output ?20mv 0 +20mv 10617-040 figure 46 . negative settling time to 0.1% , v sy = 2.7 v input voltage (2v/div) time (400ns/div) ada4500-2 v sy = 5.0v v cm = v sy /2 r l = 10k c l = 10pf dut a v = ?1 error band post gain = 20 input output ?40mv 0 +40mv 10617-042 figure 47 . positive settling time to 0.1% , v s y = 5 .0 v input voltage (2v/div) time (400ns/div) ada4500-2 v sy = 5.0v v cm = v sy /2 r l = 10k c l = 10pf dut a v = ?1 error band post gain = 20 input output ?40mv 0 +40mv 10617-043 figure 48 . negative settling time to 0.1% , v sy = 5.0 v
data sheet ada4500- 2 rev. a | page 17 of 24 t a = 25 c, unless otherwise noted. voltage noise density (nv/ hz) frequency (hz) 1k 100 10 1 10 100 1k 10k 10m 1m 100k ada4500-2 v sy = 2.7v v cm = v sy /2 10617-044 figure 49 . voltage noise dens ity vs. frequency , v sy = 2.7 v (10 hz to 10 mhz) voltage noise density (nv/ hz) frequency (hz) 1k 100 10 1 10 100 1k 10k 100m 10m 1m 100k ada4500-2 v sy = 2.7v v cm = v sy /2 10617-300 figure 50 . voltage noise density vs. frequency, v sy = 2.7 v (10 hz to 100 mhz) input referred voltage (500nv/div) time (1s/div) ada4500-2 v sy = 2.7v, a v = +100 v cm = v sy /2 10617-045 figure 51 . 0.1 to 10 hz noise , v sy = 2.7 v voltage noise density (nv/ hz) frequency (hz) 1k 100 10 1 ada4500-2 v sy = 5.0v v cm = v sy /2 10617-047 10 100 1k 10k 10m 1m 100k figure 52 . voltage noise density vs. frequency , v sy = 5.0 v (10 hz to 10 mhz) 10 100 1k 10k 100m 10m 1m 100k voltage noise density (nv/ hz) frequency (hz) 1k 100 10 1 ada4500-2 v sy = 5.0v v cm = v sy /2 10617-301 figure 53 . voltage noise density vs. frequency, v sy = 5.0 v (10 hz to 100 mhz) input referred voltage (500nv/div) time (1s/div) ada4500-2 v sy = 5.0v a v = +100 v cm = v sy /2 10617-048 figure 54 . 0.1 to 10 hz noise , v sy = 5 .0 v
ada4500- 2 data sheet rev. a | page 18 of 24 t a = 25 c, unless otherwise noted. thd + noise (%) v in (v rms) 100 10 1 0.1 0.01 0.001 0.0001 0.001 100 10 1 0.1 0.01 ada4500-2 v sy = 2.7v v cm = v sy /2 a v = +1 80khz low-pass filter r l = 10k 10617-046 figure 55 . thd + noise vs. amplitude, v sy = 2.7 v thd + noise (%) frequency (hz) 1 0.0001 0.001 0.01 0.1 10 100k 10k 1k 100 ada4500-2 v sy = 2.7v a v = +1 80khz low-pass filter r l = 10k v in = 0.7v rms 10617-050 figure 56 . thd + noise vs. frequency, v sy = 2.7 v thd + noise (%) v in (v rms) 100 10 1 0.1 0.01 0.001 0.0001 0.001 100 10 1 0.1 0.01 ada4500-2 v sy = 5.0v v cm = v sy /2 a v = +1 80khz low-pass filter r l = 10k 10617-049 figure 57 . thd + n oi se vs. amplitude , v sy = 5.0 v thd + noise (%) frequency (hz) 1 0.0001 0.001 0.01 0.1 10 100k 10k 1k 100 ada4500-2 v sy = 5.0v a v = +1 80khz low-pass filter r l = 10k v in = 1.4v rms 10617-051 figure 58 . thd + noise vs. frequency, v sy = 5.0 v
data sheet ada4500- 2 rev. a | page 19 of 24 theory of operation rail - to - rail output when processing a signal through an op amp to a load, it is often desirable to have the output of th e op amp swing as close to the voltage supply rails as possible. for example, when an op amp is driving an adc and both the op amp and adc are using the same supply rail voltages, the op amp must drive as close to the v+ and v ? rails as possible so that all codes in the adc are usable. a non - rail - to - rail output can require as much as 1.5 v or more between the output and the rails, thus limiting the input dynamic range to the adc, resulting in less precision (number of codes) in the converted signal. the ada4500 - 2 can drive its output to within a few millivolts of the suppl y rail s (see the output voltage high and output voltage low specifications in table 1 and table 2 ). the rail - to - rail output maximizes the dynamic range of the output, increasing the range and precision, and often saving the cost, board space, and added error of the additional gain stages. rail - to - rail input (rri) using a cmos nonrail - to - rail input stage (that is, a single differential pair) limits the input voltage to approximately one gate - source voltage ( v gs ) away from one of the supply lines. because v gs for normal operation is c ommonly more than 1 v, a single differential pair, input stage op amp greatly restricts the allowable input voltage. this can be quite limiting with low supply voltages supplies. to solve this problem, rr i stages are design ed to allow the input signal to r ange to the supply voltages (see the i nput voltage range specification s in table 1 and table 2 ). in the case of the ada4500 - 2 , the inputs continue to opera te 200 mv beyond the supply rails ( s ee figure 7 and figure 10). zero cross - over distortion a typical rail - to - rail input stage uses two differential pairs ( see figure 59 ). one di fferential pair amplifies the input signal when the common - mode voltage is on the high end , and the other pair amplifies the input signal when the common - mode voltage is on the low end. this classic dual - differential pair topology does have a potential dra wback. if the signal level moves through the range where one input stage turns off and the other input stage turns on, noticeable distortion occurs. figure 60 shows the distortion in a typical plot of v os ( v oltage difference betwe en the inverting and the noninverting input) vs. v cm (input voltage). 10617-103 vdd m10 m9 m12 m11 m8 m7 m6 m5 vss bias5 bias4 bias3 ?a v out vss bias2 m3 m4 vdd bias1 m1 m2 v in + v in ? figure 59 . typical pmos - nmos rail - to - rail input structure 10617-060 v cm (v) v os (v) 0 ?300 ?100 100 300 1.5 3.5 5.0 1.0 0.5 2.5 4.5 4.0 3.0 2.0 ?200 ?150 ?250 ?50 0 50 150 200 250 v sy = 5v t a = 25c figure 60 . typical input offset voltage (v os ) vs. common - mode voltage (v cm ) response in a dual differential pair input stage op amp (powered by a 5 v supply; results of approximately 100 units per graph are displayed) this distortion in the offset error forces the designer to live with the bump in the common - mode error or devise impractical ways to avoid the crossover distortion areas , thereby narrowing the common - mode dynamic range of the op amp.
ada4500- 2 data sheet rev. a | page 20 of 24 the ada4500 - 2 solves the crossover distortion problem by using an on - chi p charge pump in its input structure to power the input differential pair ( see figure 61 ). the charge pump creates a supply voltage higher than the voltage of the supply, allowing the input stage to handle a wide range of input si gnal voltages without using a second differential pair. with this solution, the input voltage can vary from one supply voltage to the other with no distortion, thereby restoring the full common - mode dynamic range of the op amp. vcp vdd vss vdd vss bias6 bias5 bias4 bias3 m1 m2 v in + v in ? ?a v out 10617-102 charge pump figure 61 . ada4500 - 2 input structure some charge pumps are designed to run in an open - loop configuration . disadvantages of th i s design include: a large ripple voltage on the output, no output regulation , slo w start - up, and a large power - supply current ripple. the charge pump in this op amp u s es a feedback network that includes a controllable clock driver and a differential amplifier . this topology results in a low ripple voltage ; a regulated output that is ro bust to line, load, and process variations ; a fast power - on startup ; and lower ripple on the power supply current. 1 the charge pump ripple does not show up on an oscilloscope ; however, it can be seen at a high frequency on a spectrum analyzer . the charge p ump clock speed adjusts between 3.5 mhz (when the supply voltage is 2.7 v) to 5 mhz (at v sy = 5 v). the noise and distortion are limited only by the input signal and the thermal or flicker noise. figure 62 shows the elimin ation of the crossover distortion in the ada4500 - 2 . this solution improves the cmrr performance tremendously. for example, if the input varies from rail to rail on a 5 v supply rail, using a part with a cmrr of 70 db minimu m, an input - referred error of 1 581 v is introduced. the ada4500 - 2 , with its high cmrr of 90 db minimum (over its full operating temperature) reduces distortion to a maximum error of 158 v w ith a 5 v supply. the ada4500 - 2 eliminates crossover distortion without unnecessary circuitry complexity and increased cost. 300 ?300 ?240 ?180 ?120 ?60 0 60 120 180 240 0 5 4 3 2 1 v os (v) v cm (v) ada4500-2 v sy = 5.0v 10617-108 figure 62 . charge pump design eliminates crossover dist ortion overload recovery when the output is driven to one of the supply rails, t he ada4500 - 2 is in an overload condition. the ada4500 - 2 recovers quickly from the overload condition . typical op amp recovery times can be in the tens of microseconds. the ada4500 - 2 typically recovers from an overload condition in 1 s from the time the overload condition is removed u ntil the output is active again. this is important in, for example, a feedback control system. the fast overload recovery of the ada4500 - 2 greatly reduces loop delay and increases the response time of the co ntrol loop (see figure 41 to figure 44). 1 oto, d.h.; dham, v.k.; gudger, k.h.; reitsma, m.j.; gongwer, g.s.; hu, y.w.; olund, j.f.; jones, h.s.; nieh, s.t.k.; " high - voltage regulation and proc ess considerations for high - density 5 v - only e 2 prom's ," ieee journal of solid - state circuits , vol. sc - 18, no.5, pp.532 - 538, october 1983.
data sheet ada4500- 2 rev. a | page 21 of 24 power - on current profile the ada4500 - 2 powers up with a smooth curr ent profile, with no supply current overshoot ( see figure 63 ). when powering up a system, spikes in the power - up current are undesirable ( see figure 64 ). the overshoot requires a designer to source a larg e enough power supply ( such as a v oltage regulator) to s upply the peak current, even though a heavier supply is not necessary once the system is powered up. if multiple amplifiers are pulling a spike in current, the system can go into a current limit state and not power up. this is all avoided with the smooth power up of the ada4500 - 2 . 10617-107 5 0 1 2 3 4 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 supply voltage (v) supply current (ma) time (s) 60 0 5 10 15 20 25 30 35 40 45 50 55 figure 63 . i sy and v sy vs. time for ada4500 - 2 wit h no spike 10617-106 5 0 60 0 5 10 15 20 25 30 35 40 45 50 55 1 2 3 4 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 supply voltage (v) supply current (ma) time (s) figure 64 . i sy and v sy vs. time with a power - up spike for systems that are frequently switching off and on, the power - up overshoot result s in excess power use. as the amplifier switches off and on, the power consumed by the large spike is repeated on each power - up, increasing the total power consumption by magnitudes. as an example, if a battery - powered sensor system periodically powers up the sensor and signal path, takes a reading , and shuts down until the next read ing, the ada4500 - 2 enable s much longer battery life because there is no excess charge being consumed at each power - up.
ada4500- 2 data sheet rev. a | page 22 of 24 applications informa tion resistance and capac itance sensor circui t the application shown in figure 65 generates a square - wave output in which the period is proportional to the value of r x and c x by e quation 1 . by fixing the c x and measuring the period of the output signal, r x can be determined . fixing r x allows for the measurement of c x . period = 4.80 r x c x ( 1 ) u 1a takes advantage of the high input impedance and large rail - to - rail input dynamic range of the ada4500 - 2 to measure a wide range of resistances (r x ) . u1b is used as a comparator; with the noninverting input swing ing between (1/12) v pos and (11/12) v pos , and the output swinging from rail to rail. because the accuracy of the circuit depend s on the propagation time through the amplifers , the fast recovery of u1b from the output overload conditions make s it ideal for this application. 10617-104 v pos u1a ada4500-2 v pos u1b ada4500-2 output r1 10k? v pos r3 100k? r2 100k? rx cx figure 65 . a resistance/capacitance sensor adaptive single - ended - to - differential s ignal converter the challenge when designing a signal path in systems that have a single voltage supply, the biggest challenge is how to represent the full range of an input signal that may have positive, zero, and negative values. by i ncluding zero in the output , the output signal must go completely to ground, which single - supply amplifier s cannot do. converting the single - ended input signal to a differential signal (through a single - ended - to - differential signal converter circuit) allows zero to be represented as the positive and negative outputs bei ng equal , requiring neither amplifier to go to ground. there are other benefits of the single - ended - to - differential signal conversion, such as doubling the amplitude of the signal for better signal - to - noise ratio, rejecting common - mode noise, and driving the input of a high precision differential adc. in addition to converting to a differential signal , the circuit must set the common - mode dc level of its output to a level that gives the ac signal maximum swing at the load (like the input to an adc). t hree key challenges are encountered often when designing a single - ended - to - differential signal converter circuit with a single supply : ? w hen the supply is limited to a single voltage, the input signal level to the circuit is generally limited to operate fr om ground to the supply voltage (v s y ). this limitation on the input dynamic range can require attenuation and/or level - shifting of the source signal before it even gets to the single - ended - to - differential signal converter. th is result s i n reduced signal - to - noise ratio (snr) and additional error. ? t he dc part of the input signal, on which the ac signal rides, is generally not known during system operation. for example , if multiple input signals from varying sources are multiplexed into the single - ended - to - dif ferential signal converter circuit, each one could have a different dc level. accommodating multiple dc input levels means that the system design must compromise the maximum allowed peak voltage of the ac part of the input so that it does not clip against the rails. ? t he system processor does n o t know what the dc level is of the original signal so it cannot make adjustments accordingly. the solution these challenges are solved with the adaptive single - ended to differential converter shown in figure 66 . this circuit operates off a single supply from 2.7 v to 5 .5 v, it automatically adjusts the dc common mode of the output to a desired level, and it provides the ability to measure the dc component of the input signal. this circuit u s es two voltage sources: a positive supply rail (v s y ) and a reference voltage (v ref ). u1a buffers the input signal, while u1b integrates that signal and feeds the integrated (dc) voltage back to u1a to center the output signal on v ref . resist ors r10 and r11 are set to equal the impedance of the resistors r8 and r9 f or a matched ac response and for balancing the effects of the bias current. the input frequency can range from 10 hz to 1 mhz. peak - to - peak amplitude of the input signal can be as l arge as v sy ? 100 mv . the dc common mode (v cm ) of the input signal can be as high as + 1.5 v sy and ? 0.5 v sy ; therefore, a system with a + 5 v supply voltage can take a common mode from as high as + 7.5 v and as low as ? 2.5 v with a signal amplitude of 5 v p - p. the wi de range of v cm above and below ground, along with a signal amplitude as large as the supply, eliminate s the need to reduce the amplitude of the input signal and sacrifice snr. w hen measuring both the ac and the dc parts of the signal, a capacitor cannot b e in the signal path. figure 66 shows examples of the voltage ranges of th e single - ended - to - differential signal converter circuit.
data sheet ada4500- 2 rev. a | page 23 of 24 besides converting the ac signal from single - ended to differential, this circ uit separates the ac and dc part of the input signal and automatically adjusts the common - mode dc level of the output sig nal to the same voltage as v ref . the output signal is then a differential version of t he input signal with its common - mode voltage se t to an optimal value (such as, ? the full - scale input range to the adc). the non inverted ac part of the signal is output at outp , and the inverted ac signal is output at outn. the differential output signal (outp to outn) is centered on the voltage applied to ref. in this design, r3 and r4 set ref to ? v pos for maximum signal peak - to - peak swing ; however, these resistors can be eliminated , and the ref input can be driven from an external source , such as a reference or the output of a digital - to - analog converte r (dac). the dc common - mode part of the input signal (v dc ) wa s measured using the voltage applied at ref and the voltage measured at the feedback (fb) output using equation 2. with v cm of the input signal known to the system, it can respond appropriately t o, for example, a situation when the common mode is getting too close to the rails. v dc = (2 fb ) ? ( ref ) ( 2 ) 10617-105 v sy outp v sy u1a ada4500-2 r1b 1k? r1a 1k? c1 100pf r2 2k? c2 10pf v sy u2a ada4500-2 r11 5k? input r6 10k? r5 10k? c5 0.01f c3 1f c7 1f c6 1f ref outn fb r10 5k? v sy r9 5k? r8 5k? v sy r4 100k? r3 100k? u2b u1b v ref v pp output v cm v pp input v cm_max = 1.5 v sy v cm_min = ?0.5 v sy v pp_max = v sy ? 0.1v examples (v sy = 5v) +2.5v 0v +5v v pp +7.5v +5v +10v ?2.5v ?5v 0v or outp outn outp outn figure 66 . single - e nded - to- d ifferential conversion circuit separates the ac and dc p art of the s ignal
ada4500- 2 data sheet rev. a | page 24 of 24 outline d imensions t o p view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index are a se a ting plane 0.80 0.75 0.70 1.70 1.60 sq 1.50 0.203 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weed 07-06-20 1 1- a pin 1 indic a t or (r 0.15) figure 67 . 8 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very, very thin, dual lead (cp - 8 - 12) dimensions shown in millimeters c o m p l i a n t t o j e d e c s t a n d a r d s m o - 1 8 7 - a a 6 0 0 . 8 0 0 . 5 5 0 . 4 0 4 8 1 5 0 . 6 5 b s c 0 . 4 0 0 . 2 5 1 . 1 0 m a x 3 . 2 0 3 . 0 0 2 . 8 0 c o p l a n a r i t y 0 . 1 0 0 . 2 3 0 . 0 9 3 . 2 0 3 . 0 0 2 . 8 0 5 . 1 5 4 . 9 0 4 . 6 5 p i n 1 i d e n t i f i e r 1 5 m a x 0 . 9 5 0 . 8 5 0 . 7 5 0 . 1 5 0 . 0 5 1 0 - 0 7 - 2 0 0 9 - b figure 68 . 8 - lead mini small outline packag e [msop] (rm - 8) d imensions shown in millimeters ordering guide model 1 temperature package description package option branding ada4500 -2a c p z -r7 ?40c to +125c 8 - lead lead frame chip scale package [lfcsp_wd] cp -8 -12 a2z ada4500 - 2acpz -rl ?40c to +125c 8 - lead lead frame chip scale package [lfcsp_wd] cp -8 -12 a2z ada4500 - 2armz ?40c to +125c 8 - lead mini small outline package [msop] rm - 8 a2z ada 4500 - 2armz - r7 ?40c to +125c 8 - lead mini small outline package [msop] rm - 8 a2z ada4500 - 2armz - rl ?40c to +125c 8 - lead mini small outline package [msop] rm - 8 a2z 1 z = rohs compliant part . ? 2012 analog devices, inc. all rights r eserved. trademarks and registered trademarks are the property of their respective owners. d10617 - 0 - 10/12(a)

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